1. Field of the Invention
The present invention relates to address counter clock signal generators, and in particular, to address counter clock signal generators for addressing base character image information for display within an on screen display (xe2x80x9cOSDxe2x80x9d) contained within a displayed screen image.
2. Description of the Related Art
An OSD character generator is a character font based generator that uses an area of programmable memory to define a page of characters. Each character is defined by an address which points to the character cell matrix stored elsewhere in memory (typically in bit-mapped form). Addressing logic then steps through the page memory on a character-by-character basis across each row. Within each row of characters, a line address counter determines which line of the character matrix is to be displayed. This is represented in FIG. 1 where, for example, the character xe2x80x9cAxe2x80x9d is shown as being part of a character cell matrix.
Each character is composed of a matrix of picture elements (xe2x80x9cpixelsxe2x80x9d) P with a set number of pixels in the horizontal direction X and a set number of lines in the vertical direction Y. As each character is addressed, the line counter addresses the line of pixels required. This line of pixels is then loaded into a serializer register at the frequency of the character clock signal, following which the pixel data is sequentially read out at the frequency of the pixel clock signal as a train of pulses.
If a sequential counter is used to generate the character line address information, each horizontal line of OSD pixels displayed on the screen will follow sequentially. In a typical monitor having multiple synchronization (xe2x80x9cmulti-syncxe2x80x9d) capabilities, the number of overall image lines displayed on the screen can vary depending upon the display format, or mode, being used.
Referring to FIG. 2, for example, VESA specifies several different modes of operation. As the monitor ensures that the height of the displayed image remains the same (typically 200 millimeters for a 17 inch CRT), the height of a single pixel row will decrease since the total number of vertical lines within the image increases. Therefore, if an OSD character has a fixed number of lines C (where typically C=18), then the character height will be reduced as the number of scan lines increases.
The OSD generator compensates for this variation in pixel height by increasing the number of lines within the character so as to maintain a constant character height. However, it is desirable that some control be allowed over the height of the OSD character by allowing variations in the number of character lines. Accordingly, since the number of lines that actually define the base character are fixed, the only way to increase the number of lines within the OSD character image is to repeat one or more of such defined lines. For example, to increase the displayed number of character lines from 18 to 20 lines, it becomes necessary to display two of the lines twice.
Therefore, in order to provide OSD characters of variable heights, it becomes necessary to use a character line address generation technique in which lines within the character can be repeated according to some predetermined algorithm. Additionally, such OSD addressing system must be capable of generating interlaced video in order to operate with interlaced image formats. (As is well known, in an interlaced image format, two successive fields are used to create one frame, with the even line numbers being displayed within the even field and the odd line numbers being displayed within the odd field. By displaying the odd lines and then the even lines in quick succession, the viewer is made to believe that the image is being refreshed at the field rate as opposed to half of the field rate.)
Referring to FIG. 3, in order to maintain a constant character height H, the number of lines N in an OSD character should, ideally, vary in direct proportion to the total number of lines V within the image. Three different example character heights are shown (Heights 1, 2 and 3). The minimum number of lines per character is indicated as being 18 since this corresponds to the number of lines in the basic character cell with no repeated lines.
Referring to FIG. 4, it can be seen how the displayed number of lines in an 18-line character cell must be increased for different numbers of image scan lines, where 320 image lines corresponds to the base 18 character lines (Height 2 within the graph of FIG. 3).
As a practical matter, almost any number of displayed image lines V may be displayed within an image provided that the OSD character line duplication system is capable of accounting for this when it is desired to maintain a constant character height. However, in actual practice, it has become acceptable within the display industry to allow some variation in OSD character height (e.g., +/xe2x88x9215% about the nominal base character height). This allows the line address duplication system to use the same duplication algorithm within bands of image line counts.
For example, FIG. 4 indicates that if 36 character lines are required within a 640 image line display, then 40 character lines are required for a 704 image line display. Therefore, 39 lines would theoretically be required for a 700 line image. However, in practice it may be acceptable to use the 36 character line repetition sequence for any number of image lines between 640 and 704 image lines. While this xe2x80x9croundingxe2x80x9d approximation may create potential errors in the actual character heights compared to the ideal character heights, such errors are generally acceptable. (In this last example, the error would result in a variation of character height of less than +/xe2x88x924% about the average period.)
It is possible to determine which lines of character image information should be repeated by using the ideal formula, shown below as Equation 1, to calculate the address for each character line, where TRUNC is a function which truncates to the integer value, H is the horizontal line number in the range of zero through N within the displayed character row, C is the number of lines within the base character matrix, and N is the required number of displayed character lines:                               Character          ⁢                      xe2x80x83                    ⁢          Line          ⁢                      xe2x80x83                    ⁢          Address                =                  TRUNC          ⁡                      [                                          H                *                C                            N                        ]                                              (        1        )            
The resulting address information is shown in FIG. 5, where it can be seen, for example, that all the even numbered character lines are repeated for an image with a total number of image lines in the range of 486-587 lines. In this example, an arbitrary number of 18 character rows has been chosen for illustration, with each row having 18 lines within the character matrix. Thus, the lowest number of image lines that can be displayed without losing any OSD character lines is 18xc3x9718=324. This number can also be expressed by a variable Z, where Z is equal to the total number of OSD lines to be displayed within the vertical image space.
In this example, with Z=324, every line is displayed once in the 324 line mode. As the number of image lines is increased for a given value of Z, character lines are selectively repeated in order to maintain the same character height. At 648 image lines, i.e., 2*Z, each OSD character line must be displayed twice. As mentioned above, in order to simplify the system, the image line modes can be grouped into intervals. A suitable grouping is found by dividing the range between the 324 and the 648 line modes into four discrete equal intervals. For example, in this case, the interval is equal to 324/4=81. More generally, this interval can be expressed as a variable Y, where Y=Z/4. Thus, for example, image modes with a number of image lines in the range of 324-404 can use the same line repetition sequence with acceptable character height variation.
In a typical OSD character generator, the character line address generator is a binary counter which takes a synchronization pulse from the horizontal scan system for the display monitor. The counter then counts to the maximum line number (e.g., 18) and then resets itself to address the next row of characters. One way of repeating character lines is by selectively blanking the input pulses to the counter at the start of the line. Doing so produces a lower frequency pulse train, thereby causing the counter to count at a slower rate. For example, each character line can be repeated by simply blanking every alternate pulse.
Generally, to achieve the desired addressing, the average input frequency FA to the counter must be as represented by Equation 2 below (expressed as an average since the pulses must be synchronized to the horizontal line frequency), where FH is the horizontal line frequency, C is the number of lines within the base character matrix, and N is the required number of displayed character lines:                               F          A                =                                            F              H                        *            C                    N                                    (        2        )            
One conventional technique used to divide the incoming frequency by the appropriate factor is to use an analog or digital phase lock loop to generate the lower frequency. This method, however, has disadvantages of relatively high cost and high circuit complexity.
Another conventional technique is to use some form of arithmetic computation to calculate each character line address. Such technique repeatedly adds a binary number once every line period to a number contained within an accumulator register. When the sum overflows the register, the overflow bit is then used to clock the character address counter. While this technique may be appealing in some applications, it does have two distinct disadvantages. One disadvantage is the requirement of the additive integer to vary with the inverse of the number of displayed lines, thereby requiring either the external microprocessor or microcontroller to measure the line count and create the binary reciprocal, or requiring some complex logic within the OSD generator to create the binary reciprocal. Another disadvantage is the requirement of an arithmetic unit within the OSD generator to compute the address. Such arithmetic units are relatively large circuits and costly to implement.
Accordingly, it would be desirable to have a technique for generating a stream of pulses for a character line address counter at a close approximation to the desired frequency without requiring intervention by a microprocessor, microcontroller or complex arithmetic unit. Further, it would be desirable to use the image line count directly to allow the height of the displayed OSD characters to be set in accordance with a single parameter and remain constant thereafter. Further still, it would be desirable to achieve these goals with a design which is relatively low in complexity and, therefore, low in cost to implement.
In accordance with the present invention, an apparatus including a character line address counter clock signal generator and a method are provided for generating a character line address counter clock signal for an on screen display circuit used to selectively display a character image within an on screen display contained within a displayed screen image. The displayed character image has a scaled number of character image lines which is proportionately larger than a base number of character image lines for a base character image, the displayed screen image has a scaled number of screen image lines which is proportionately larger than a base number of screen image lines for a base screen image, and the proportionality of the scaled and base numbers of character image lines is substantially equal to the proportionality of the scaled and base numbers of screen image lines.
In accordance with one embodiment of the present invention, the character line address counter clock signal generator includes frequency divider circuits and a signal selection circuit. One frequency divider circuit is configured to receive and divide a horizontal synchronization signal by a first divisor and in accordance therewith provide a first quotient signal which corresponds to an integer R. Another frequency divider circuit, coupled to the first frequency divider circuit, is configured to receive the first quotient signal and in accordance therewith receive and divide an input clock signal by a second divisor which equals the integer R and in accordance therewith provide a second quotient signal, wherein the input clock signal and the horizontal synchronization signal have respective frequencies which are proportional by an integer factor of unity or more. The signal selection circuit, coupled to the frequency divider circuits, is configured to receive the first quotient signal and in accordance therewith receive and select one of the input clock and second quotient signals and in accordance therewith provide the character line address counter clock signal, wherein the scaled number of character image lines includes first and second alternating subsets of selected ones of the base character image lines which are used R times and R+1 times, respectively.
In accordance with another embodiment of the present invention, the character line address counter clock signal generator includes frequency divider circuits, a signal selection circuit and a divisor control circuit. One frequency divider circuit is configured to receive and divide a horizontal synchronization signal by a first divisor and in accordance therewith provide a first quotient signal which corresponds to an integer R and a second quotient signal which corresponds to an integer I. Another frequency divider circuit, coupled to the first frequency divider circuit, is configured to receive a divisor control signal and the first quotient signal and in accordance therewith receive and divide an input clock signal by a second divisor which alternately equals the integer R and another integer R+1 and in accordance therewith provide a third quotient signal, wherein the input clock signal and the horizontal synchronization signal have respective frequencies which are proportional by an integer factor of unity or more. The signal selection circuit, coupled to the frequency divider circuits, is configured to receive the first quotient signal and in accordance therewith receive and select one of the input clock and third quotient signals and in accordance therewith provide the character line address counter clock signal, wherein the scaled number of character image lines includes first and second alternating subsets of selected ones of the base character image lines which are used R times and R+1 times, respectively, in accordance with an interval corresponding to the integer I. The divisor control circuit, coupled to the frequency divider circuits, is configured to receive the second quotient signal and couple to and receive from a character line address counter circuit character line address signals which correspond to character line addresses for the base character image lines and in accordance therewith provide the divisor control signal.
In accordance with still another embodiment of the present invention, the method includes the steps of:
dividing a horizontal synchronization signal by a first divisor and in accordance therewith generating a first quotient signal which corresponds to an integer R;
receiving the first quotient signal and in accordance therewith receiving and dividing an input clock signal by a second divisor which equals the integer R and in accordance therewith generating a second quotient signal, wherein the input clock signal and the horizontal synchronization signal have respective frequencies which are proportional by an integer factor of unity or more; and
receiving the first quotient signal and in accordance therewith receiving and selecting one of the input clock and second quotient signals and in accordance therewith generating the character line address counter clock signal, wherein the scaled number of character image lines includes first and second alternating subsets of selected ones of the base character image lines which are used R times and R+1 times, respectively.
In accordance with yet another embodiment of the present invention, the method includes the steps of:
dividing a horizontal synchronization signal by a first divisor and in accordance therewith generating a first quotient signal which corresponds to an integer R and a second quotient signal which corresponds to an integer I;
receiving a divisor control signal and the first quotient signal and in accordance therewith dividing an input clock signal by a second divisor which alternately equals the integer R and another integer R+1 and in accordance therewith generating a third quotient signal, wherein the input clock signal and the horizontal synchronization signal have respective frequencies which are proportional by an integer factor of unity or more;
receiving the first quotient signal and in accordance therewith selecting one of the input clock and third quotient signals and in accordance therewith generating the character line address counter clock signal, wherein the scaled number of character image lines includes first and second alternating subsets of selected ones of the base character image lines which are used R times and R+1 times, respectively, in accordance with an interval corresponding to the integer I; and
receiving the second quotient signal and receiving from a character line address counter circuit character line address signals which correspond to character line addresses for the base character image lines and in accordance therewith generating the divisor control signal.
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.